This disclosure is related to the field of semiconductor and electrical systems. In particular, this disclosure includes systems and components including, for example, various embodiments of a new capabilities metal oxide semiconductor (NCMOS). Methods of manufacturing and operation are also included.
Metal Oxide Field Effect Transistors (MOSFETs) are used because of their fast switching, low power capabilities. FIG. 1 represents a simplistic vertical cross-sectional view of an N-channel MOSFET 1 design/layout where the structure is sliced parallel to a source and drain along the length of a channel (for reference, see FIG. 2, orientation of cutline AB used in FIG. 1). FIG. 3 represents prior art, a simplistic vertical cross-sectional view of a P-channel MOSFET 3 design/layout where the structure is sliced parallel to a source and drain along the length of a channel (for reference, see FIG. 4, orientation of cutline AB used in FIG. 3). An exemplary N-channel MOSFET 1 as shown in FIG. 1 uses a P-type substrate 115; whereas, an exemplary P-channel MOSFET 3 as shown in FIG. 3 uses an N-type substrate 135. A conductive layer contacting a bottom of the substrate forms a substrate contact 117 (for N-channel) or substrate contact 137 (for P-channel). At top of exemplary substrate 117 or 137, a region of opposite doping 105, 107 (for N-channel) and 125, 127 (for P-channel) is implanted/diffused to form a doped region (hereinafter referred to as body) (e.g., N-channel devices use N-type body 105, 107 and P-channel devices use N-type body 125, 127). To ensure contact to body regions, a higher doped region can be implanted/diffused into the exemplary body (not shown). Once doped regions are formed (e.g., P-type bodies 105, 107 or N-type bodies 125, 127), a conductive layer can be deposited to make drain contact 101 or 121 and source contact 103 or 123 forming a portion of an electrical conductive path (shown as dashed line through these areas) for an electrical power supply (not shown). A dielectric material (e.g., a gate oxide 109 or 129) can be placed on top of substrate region (e.g., P-type substrate 115 or N-type substrate 135) and over/between body regions (e.g., N-type body regions 105, 107 or P-type body regions 125, 127). Referring to FIG. 1, a MOS gate contact 111 is formed by placing a conductive layer on top of gate oxide 109. A region separated between N-type body regions 105, 107 but underneath gate oxide 109 defines a semi-conductive channel region (SCR) 113. Referring to FIG. 3, a MOS gate contact 131 is formed by placing a conductive layer on top of gate oxide 129. A region separated between P-type body regions 125, 127 and underneath gate oxide 129 defines a semi-conductive channel region (SCR) 133. Dashed arrow lines represent an electrical conductive path that is formed during operation of FIGS. 1 and 3 MOSFETs.
Various modifications/improvements in the design, layout, and fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs) have been made to enhance electrical and radiation performance (e.g., lower power, faster switching, enhanced radiation hardness, etc.). Radiation issues have been discovered and significant research has been devoted to resolve specific radiation issues (e.g., total ionizing dose (TID) and single-event gate rupture issues).
Under normal MOSFET operation, application of an appropriate gate voltage (a gate voltage greater than MOSFET's gate threshold voltage) forms a conducting path between source and drain (forming a channel region along a surface) allowing current to flow (MOSFET is turned on). Higher gate voltage above threshold voltage equates to higher current flow. An effect of TID is to trap charge, e.g. positive charge, within a gate oxide, which in turn induces a shift in MOSFET gate threshold voltage (e.g., gate threshold voltage changes with TID). If this TID-induced threshold voltage shift becomes sufficiently large, the radiation induced trapped charge interferes with functional behavior of the MOSFET's gate (e.g., the MOSFET begins to act like electrons are on its MOSFET gate) gradually rendering the MOSFET non-functional (e.g., N-channel MOSFET cannot be turned off while P-channel MOSFET cannot be turned on without exceeding its electrical specification). Methods exist to help resolve TID issues exhibited by MOSFETs. One method is to decrease the thickness of a MOSFET's gate oxide (thinner gate oxide trap less charge) but a thinner gate oxide makes a MOSFET more susceptible to SEGR and increases gate capacitance. Another method is to control quality of gate dielectric material but higher quality equates to higher costs and lot-to-lot variability. Another method is to exceed a gate voltage specification that drives a MOSFET (gate voltage to turn-on or turn-off a MOSFET) but the gate threshold voltage can shift beyond safe operating voltages.
FIG. 5 shows a cross-sectional view of a simplified design/layout of an exemplary P-channel Junction-Field-Effect Transistor (JFET) 5 with the JFET structure cut perpendicular to drain contact 141 and source contact 143 along the JFET gates 149, 151. FIG. 6 shows a cross-sectional view of a simplistic design/layout of an exemplary N-channel JFET, with the JFET structure cut perpendicular to drain contact 161 and source contact 163 along the JFET gates 169, 171. A JFET uses a reverse-biased P-N junction to control current flow by modulating the depletion field lines 155 or 175 within the Semi-conductive channel region (SCR) 157 or 177 (a higher reverse voltage applied to PN junction extends the depletion field lines further outward restricting current flow in SCR 177). P-Channel JFET uses a P-Type Substrate 153 and N-Channel JFET uses an N-Type Substrate 173. A conductive layer can be deposited onto opposite ends of substrate forming a drain contact 141 (for P-channel) or 161 (for N-channel) and a source contact 143 (for P-channel) or 163 (for N-channel). Toward a middle of 153 (for P-channel) or 173 (for N-channel), a region is implanted/diffused with opposite doping of substrate (P-Channel uses an N-type Body 145, 147; whereas, N-Channel uses P-Type Body 165, 167) forming a PN junction between body and substrate regions. A conductive layer is deposited onto these opposite doped regions to form JFET gate contacts 149, 151 (for P-channel) or 169, 171 (for N-channel).
Unlike a MOSFET, a JFET exhibits a natural TID radiation hardness. TID effects in a MOSFET are caused by radiation-induced trapped charge in gate oxide interfering with modulation of semi-conductive channel region; whereas, a JFET does not employ a dielectric material to modulate semi-conductive channel region eliminating the effect of radiation-induced trapped charge.
Some applications involving radio-frequency (RF) applications such as RF mixers, RF amplifiers, RF gain control, and RF detectors may employ two individual transistors (e.g., MOSFETs) to perform an intended function. If an electrical circuit uses two transistors to accomplish an intended function, there are added costs and weight and requires more space when compared to a single transistor option. FIG. 7 shows a simplified circuit design using a dual gate transistor and the same design using two transistors to demonstrate how a dual gate transistor can be used in an actual circuit design. A dual gate transistor can be used in many other RF type applications. Note, the FIG. 7 circuit shows a dual gate scheme which requires a different architecture than is shown in FIGS. 1-6 as there would be a different top view showing two gate contacts and some other differences. Presently, dual-gate MOSFETs can be built by packaging two MOSFETs into a hybrid-type package where the two MOSFETs are placed in series but this implementation does not address radiation effects and increases overall cost, weight and size. Another implementation is to place two MOSFETs in series using a monolithic type layout. Again, this implementation does not address radiation effects.
Embodiments of the invention provide improvements to address various disadvantages and provide desired improvements. For example, one embodiment of the invention, such as an exemplary NCMOS, can include a layout/design of an innovative structure which allows a drain-to-source current to be controlled by a MOS gate as well as be controlled by a side JFET gate. An exemplary NCMOS can be fabricated as a monolithic device (merging aspects of MOSFET functions with a MOS gate and JFET gates into a monolithic device). One embodiment's basic fabrication steps (design/layout) of an exemplary NCMOS can include implanting/diffusing the JFET gates in conjunction with elements of manufacturing of a MOSFET gate. Exemplary embodiments of the invention, e.g., NCMOS, can also enhance operational performance in a TID radiation environment. Existing MOSFETs can be prone to TID-induced threshold voltage (VTH) shifts from ionizing radiation environments that can lead to functional failure. An exemplary embodiment's independent JFET Gate can provide a radiation-hardened-by-design (RHBD) approach if MOS gate functionally fails from TID effects by using side JFET gates to control current flow beyond operational failure point of MOS gate (e.g., an exemplary improved side JFET gate allows the exemplary structure to control current in the semi-conductive channel region even after the MOS gate becomes non-functional from TID-induced threshold voltage shifts). Additionally, an exemplary NCMOS can be useful in RF type applications such as mixers, gain control, amplifiers, and detectors because the exemplary device employs a second independent gate to control current flow in the semi-conductive channel region. A variety of MOSFET gate oxide lens structures as well as a current leakage preventing or mitigation structures are also provided. Control systems are also provided to operate various embodiments of the invention in a variety of modes of operation. Methods of manufacturing and operation are also provided.
Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of the illustrative embodiment(s) exemplifying some best modes of carrying out the invention as presently perceived.